Reliability of Analog-to-Digital Sigma-Delta Converters

Due to the continuously scaling down of CMOS technology, system-on-chips (SoCs) reliability becomes important in sub-90 nm CMOS node. Integrated circuits and systems applied to aerospace, avionic, vehicle transport and biomedicine are highly sensitive to reliability problems such as ageing mechanisms and parametric process variations. Novel SoCs with new materials and architectures of high complexity further aggravate reliability as a critical aspect of process integration. For instance, random and systematic defects as well as parametric process variations have a large influence on quality and yield of the manufactured ICs, right after production. During ICs usage time, time-dependent ageing mechanisms such as negative bias temperature instability (NBTI) and hot carrier injection (HCI) can significantly degrade ICs performance. Design-for-reliability (DFR) aims to consider reliability problems during the design phase of integrated circuits (ICs) and systems. Coping with reliability issues has significant importance in terms of both cost reduction and product time-to-market. In order to realize design specification at required reliability levels, it is necessary to carry out research work on defects modeling, reliability methodology development, reliability analysis/simulation, failure prediction and reliability optimization/enhancement. Previous reliability-aware work during SoCs design phase can provide useful information to ICs designers, which help them to avoid pessimistic design and reserve appropriate design space to failure boundary. This thesis concentrates on reliability-aware methodology development, reliability analysis based on simulation as well as failure prediction of CMOS 65 nm analog and mixed signal (AMS) ICs. Sigma-Delta (Σ∆) modulators are concerned as the object of reliability study at system level. A hierarchical statistical approach for reliability is proposed to analysis the performance of Σ∆ modulators under ageing effects and process variations. Statistical methods including correlation analysis, design of experiments, regression analysis and response surface modeling are combined into this analysis flow. Based on 65 nm CMOS technology, some typical analog circuits are studied with reliability-aware simulation methodologies. A co-evaluation reliability analysis flow for ageing effects and process variations is proposed and applied to current mirrors and a dynamic comparator. A reliability simulation approach based on Pareto fronts is presented and used to a classic miller operation amplifier. Ageing degradation in a non-overlapping clock distributor is studied. At system level, an ultra low power 400 Hz second order low-pass continuous-time (CT) Σ∆ modulator is designed for cardiac pacemaker application. The reliability study concludes that in low power, low order CT Σ∆ modulator, feedback loop is less reliable than analog loop filter. DAC is the most sensitive building block. Comparing with HCI, NBTI is the dominate effect in the designed CT Σ∆ modulator. Besides, a 125 kHz third order CT Σ∆ modulator is implemented to study clock jitter effects. It presents that NBTI mechanism can induce clock jitter in clock distributor for CT Σ∆ modulator. As a consequence, modulator performance is severely degraded due to NBTI effect. Moreover, reliability-aware design of CT Σ∆ modulator is summarized.